The so-called “silicon revolution” brought about the development of faster and larger computers beginning in the early 1960s with predictions of rapid growth because of the increasing numbers of transistors packed into integrated circuits with estimates they would double every two years. Since 1975, however, they doubled about every 18 months.
An active period of innovation in the 1970s followed in the areas of circuit design, chip architecture, design aids, processes, tools, testing, manufacturing architecture, and manufacturing discipline. The combination of these disciplines brought about the VLSI era and the ability to mass-produce chips with 100,000 transistors per chip at the end of the 1980s, succeeding the large scale Integration (“LSI”) era of the 1970s with only 1,000 transistors per chip. (Carre, H. et al. “Semiconductor Manufacturing Technology at IBM”, IBM J. RES. DEVELOP., VOL. 26, no. 5, September 1982). Mescia et al. also describe the industrial scale manufacture of these VLSI devices. (Mescia, N. C. et al. “Plant Automation in a Structured Distributed System Environment,” IBM J. RES. DEVELOP., VOL. 26, no. 4, July 1982). These VLSI devices have now been advanced to the next level of miniaturization referred to as Ultra-Large Scale Integrated (ULSI) microelectronic circuits.
The release of IBM's Power6™ chip in 2007, noted this ULSI “miniaturization has allowed chipmakers to make chips faster by cramming more transistors on a single slice of silicon, to the point where high-end processors have hundreds of millions of transistors.” (http://www.nytimes.com/reuters/technology/tech-ibm-ower.html?pagewanted=print (Feb. 7, 2006)).
Technology scaling of semiconductor devices to 90 nm and below has provided many benefits in the field of microelectronics, but has introduced new considerations as well. While smaller chip geometries result in higher levels of on-chip integration and performance interconnect structures the nano structures employed introduce new considerations that the industry has to address such as protecting nano structure interconnects in BEOL structures such as ULSI microelectronic circuits.
Traditional semiconductor devices, consisting of aluminum and aluminum alloys have been used as interconnect metallurgies for providing electrical connections to and from devices in BEOL layers. While aluminum-based metallurgies have been the material of choice for use as metal interconnects in the past, aluminum no longer satisfies the requirements for increased circuit density and speed in semiconductor devices as the scale of devices decreases. More advanced manufacturing therefor employs copper as a replacement for aluminum, because of its lower susceptibility to electromigration (EM) failure and its lower resistivity as compared to aluminum.
Since the 1960's electromigration (EM) has been identified as significant metal failure mechanisms in semiconductor interconnect structures, especially for very large scale integrated (VLSI) circuits and manufacturing as well as ultra large scale integrated (ULSI) circuits and manufacturing. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip, which the industry refers to as time-dependent-dielectric-breakdowns (TDDB's). EM, results from voids created inside the metal conductors of an interconnect structure due to metal ion movement caused by the high density of current flow.
Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction to the bottom of the metal interconnect, which eventually results in a circuit dead opening.
Circuit interconnects comprising vias known in the art contain a copper core surrounded by a liner to protect against EM, stress migration and TBBD breakdown caused by minimization of circuits and concomitant decreases in wire dimension that brings about increases in current density.
Liner layers and capping layers are also used in copper interconnect technology to prevent corrosion of the copper wires by sealing the top surfaces of the wires between wiring levels. Again, as wire dimensions decrease, current density increases and the “weakest” sites for resisting EM failure are the liner layer and the capping layer copper interface. Metal liner layers and capping layers improve EM performance but at the cost of increased copper corrosion.